It is essential when designing and developing integrated circuits to test the design of the circuit before the circuit is manufactured. This testing is done by simulating how a circuit built to a particular design will operate. The traditional method of logic simulation is to use a software simulator running on a conventional (non parallel) computer. A problem with this method, however, is that the performance of the simulator is usually millions of times slower than the actual performance of the hardware being simulated. This problem is magnified as the size of the chip becomes larger to the point that simulation testing of the current generation of Very Large Scale Integration (VLSI) circuits is becoming impractical.
One solution to this problem is to use special purpose computers to carry out the simulation. These special purpose computers are parallel processors, typically with up to 256 Central Processor Units (CPUs). Special software prepares the logic being simulated so that the processors may work on it in parallel. These systems are extremely expensive, however, in some cases costing millions of dollars.
An alternative less expensive solution which has been suggested is to hard wire programmable logic arrays (PLAs) into simulated circuits. These are integrated circuits that may be programmed or personalized in a few minutes to perform any logical function or combination of logical functions that may be desired. Known PLAs may be programmed to perform the desired function by the use of fusible links or electrical programming techniques such as those used with Electrically Programmable Read Only Memories (EPROMS). Such programmable logic devices have a much lower density than the VLSI integrated circuits they are simulating, though, and so many tens or possibly hundreds of PLAs may be needed to simulate one VLSI integrated circuit.
Another problem with the above approach is the large number of interconnections that have to be made between the PLAs, with each interconnection scheme designed specifically to the hardware being simulated. In the past, interconnections have been hand-wired which is not only extremely time consuming and error prone but also has the result that each simulator is unique to the hardware being simulated and cannot easily be reused. In addition, the control of the wiring and its documentation presents a problem of a similar size to the design and control of the integrated circuit itself. Yet another problem is ensuring that the designs of the simulator and the simulated integrated circuit remain in step as the design of the integrated circuit is modified. Naturally, all the aforementioned problems associated with hand-wired simulators are magnified as the size of the circuits being simulated increases.